How To Draw Waveform Of An Arithmetic Circuit Function Table
tabular array of Contents
Background introduction
Tool introduction
case report:
Case number ane
Waveform of even frequency-dividing circuit (taking frequency-dividing circuit as an case)
Odd frequency sectionalization (5 frequency division equally an example)
Case two
Conclusion
Background introduction
Today, when I turned to the web to learn most FPGA, I accidentally turned to a tool for cartoon waveforms, which angry my interest. Sometimes I need to draw waveforms. Drawing past hand is very troublesome and not standard, and it is difficult to align. And it takes a lot of fourth dimension. Sure plenty, the predecessors take gone through this procedure and wrote a tool to solve this problem. There is really a feeling of worship. I experience that I am really a dish. What I need to learn is too Many, many ideas, offset acquire how to use this tool. Draw some basic waveforms.
This web log mail uses ii cases to illustrate how to depict a waveform. Both of these cases are weblog posts that I take written before. Since the mitt drawing of the waveform is not standard (I do not have a ruler), I did not draw, just straight simulated Out, this is not conducive to the principle analysis, and today to amend. Past the way, I learned how to use this tool.
Tool introduction
First download the download accost of the tool:Wavedrom
There are 4 options at the meridian, the first is the tutorial (tutorial), click to enter, there are software or tools to use, syntax, etc.
The 2d is the Editor (Editor), click to enter, you tin write waveforms online, without downloading software, of course, people accept done the software, software on various platforms, actually admire information technology.
The third is source. Click to enter the diverse source files of this open source project. There are all the things you lot want to know, depending on whether yous can sympathize it.
The beginning detail at the bottom is the Download editor, which can be edited offline.
I will check the other ones myself, I will not introduce them.
Then my weblog case is posted:
[FPGA] Crossover circuit blueprint (Verilog HDL design) (Censor blog post)
Module six counter and module 10 counter (Verilog HDL language design) (Modelsim simulation and ISE synthesis)
The post-obit code is the default sample lawmaking of this tool. It is offset posted for general understanding, visit and visit:
{signal: [ {name: 'clk', wave: 'p.....|...'}, {name: 'dat', wave: 'x.345x|=.x', information: ['caput', 'body', 'tail', 'data']}, {name: 'req', wave: '0.1..0|one.0'}, {}, {proper name: 'ack', wave: 'i.....|01.'} ]} The waveform described by this code is:
From the lawmaking, information technology can be said that it is almost clear at a glance, it is piece of cake to get started, and the drawn waveform is also very cute and simply.
Although the lawmaking is elementary, the details still need to be advisedly studied, find a few more than cases to practice, to achieve the purpose of proficiency.
example study:
Case number one
Waveform of even frequency-dividing circuit (taking frequency-dividing circuit every bit an instance)
By default, you have read this blog post,Frequency segmentation circuit designIt doesn't matter if you don't watch it, I'll only say something more straightforward.
In this blog mail, an even frequency divider circuit is implemented. The principle is to count the rise edge of the clock and start counting from 0 to 4 (equivalent to 5 clock cycles). The divided clock clk_div flips once.
The circuit diagram obtained by functional simulation in Modelsim is as follows:
Below I will draw a schematic diagram similar to this:
First wait at the sample lawmaking provided by the software:
{signal: [ {name: 'clk', wave: 'p.....|...'}, {proper name: 'dat', wave: 'x.345x|=.x', information: ['head', 'body', 'tail', 'data']}, {proper noun: 'req', wave: '0.1..0|one.0'}, {}, {name: 'ack', wave: '1.....|01.'} ]} As can exist seen from the sample code, the overall framework of this waveform description linguistic communication is as follows:
{signal: [ ]} Fill the 2 square brackets with the waveform you demand to describe. Start, the clock waveform is described equally follows:
{indicate: [ {name: 'clk', wave:'p...........|...'}, ]} The clarification of each waveform is in a brace. Don't forget that there is a comma (,) at the end of the brace. There must be a '' afterwards the proper noun: and wave:. The relevant information is written inside the single quotes, such as the waveform name ( proper name), in wave:'p...', p represents a clock cycle, and the following betoken is the repetition of p. If there are several points, it is repeated several times, and p is counted once
In wave:'p...|...', | means that a series of clocks have been omitted and are not drawn.
The waveform described by the code above is:
Of form, you can likewise add a ascension edge logo, but supercede the p in the code with a majuscule P (Positive), as follows:
{signal: [ {proper noun: 'clk', wave:'P...........|...'}, ]} The waveform described is every bit follows:
Add together a count beneath, start counting from 0, count to four, and then clear the counter:
{signal: [ {name: 'clk', wave:'P...........|...'}, {name: 'cnt', wave:'============|===',information:['0','1','2','iii','4','0','i','2','iii','4','0','1','2','3','4']}, ]} The waveform described is:
As for how to write it, the number box in the = lawmaking in the wave, and the following information is used to make full the data. Come across below:
This description is very articulate.
Add together a frequency-divided clock below, and flip in one case in v clock cycles:
{signal: [ {name: 'clk', moving ridge:'P...........|...'}, {proper name: 'cnt', moving ridge:'============|===',data:['0','ane','2','3','4','0','one','ii','3','4','0','1','2','3','iv']}, {proper noun: 'clk_div10', moving ridge:'0....1....0.|1..'}, ]} With the above foundation, I gradually started to become started. The waveform described by this code is:
This is the frequency division by ten. The clock cycle of clk_div10 is x times that of clk, and the frequency is ane/10 of it, which is also the meaning of frequency division by x.
Odd frequency segmentation (five frequency division as an example)
The simple language used to draw the frequency division excursion waveform diagram has been finished above, the waveform diagram of the frequency division circuit five is directly fatigued below.
First briefly explain the principle:
If it is a divide-by-5 circuit with a 50% duty cycle, then the divided clock clk_div5 needs to be flipped in one case in ii.5 clock cycles of the reference clock clk. How can information technology be flipped once in ii.5 clock cycles?
This needs to generate a clock clk1 which is completely opposite to clk. This clock is 180° out of stage with clk, and so count the ascent edges of the ii clocks to 4, the initial value of the counter is 0, so information technology represents 2.5 clk clocks bike.
And look at the picture below:
It can exist seen from the figure that both the rising edges of clk and clk1 are counted, and when the count reaches iv, clk_div5 is flipped once, so that a frequency sectionalisation circuit of 5 is realized.
The lawmaking describing this waveform is:
{ signal: [ { proper name: "clk", wave: "P........", period: 2 }, { proper name: "clk1", wave: "n........", period:2 }, { name: "cnt", wave: "==================", information: "0 1 2 iii 4 0 1 ii iii 4 0 1 2 3 4 0 ane two" }, {}, { proper name: "clk_div5", wave: "0....1....0....ane.." }, ]} The essence of this picture is to arrange the period and phase, see the post-obit film:
Without too much explanation, information technology should be understandable. Information technology should exist based on the source lawmaking.
What if the duty ratio is 3:2? How to depict a waveform?
It is also very unproblematic, that is, the clk is flipped once in 3 cycles, and so flipped again in 2 cycles, and then flipped again in 3 cycles, and so it can be cycled in turn:
The description code is:
{indicate: [ {proper name: 'clk', moving ridge:'P...........|'}, {name: 'cnt', moving ridge:'============|',data:['0','1','2','0','1','0','ane','2','0','i','0','1']}, {name: 'clk_div5', wave:'0..ane.0..1.0.|'}, ]} Case 2
This example is the modulo x counter, see the original blog post:Module 6 counter and module 10 counter (Verilog HDL language design) (Modelsim simulation and ISE synthesis), This waveform is much easier to describe, Quan Dang practice hands:
When the rise edge of each clock comes, it counts once, and the counter is cleared after counting to 9.
Directly to the flick:
Code:
{signal: [ {name: 'clk', wave:'p...........|'}, {name:'cnt', moving ridge:'============|',information:['Reset 0','1','ii','3','4',' 5','6','7','8','9','0','1']}, ]} Conclusion
The so-called learning, temporarily learning these, when you use other functions, continue to study chant, anyhow, at this moment has met the demand to depict the bones waveform diagram.
Last posted, tutorial:Hitchhiker'due south Guide to the WaveDrom
Hitchhiker'due south Guide to the WaveDrom (Part 2)
Finally posted the online editing interface again:
WaveDrom Editor
Source: https://programmersought.com/article/89143926448/
Posted by: clarklects1948.blogspot.com
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